Finite state machines can be specified in a variety of ways. One way is to use HDL, such as ABEL or VHDL. The ABEL tutorial explains how the STATE_DIAGRAM, IF-THEN-ELSE or the  TRUTH_TABLE construct in ABEL can be used to fine state machines. Examples of both a  Mealy and a  Moore machine have been discussed. The Xilinx Foundation tools provide an alternative method to specify a state machine. In order to use the State Editor, one must have XABEL or X-VHDL installed. The State Editor allows you to define a state diagram using a graphical description and to convert the graphical description in either ABEL or VHDL.

In order to show the use of the State Editor, we will implement the same  sequence detector that we used to illustrate the use of ABEL to define a state machine. We will implement two variations of the same sequence detector - one implemented as a Mealy machine and another as a Moore machine.

The sequence detector recognizes the following input bit sequence X: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. In case we are implementing a Mealy machine, the output is associated with the transitions as indicated on the following state diagram.

In the following sections we will explain how to define the above state diagram using the State Editor. First one has to  create a new project (or use an existing project). For help with the State Editor go to HELP -> FOUNDATION HELP CONTENTS -> STATE EDITOR.

1. Creating a State Machine Macro

1. In the Project Manager Flowchart, click on the State Editor button or go to TOOLS -> DESIGN ENTRY -> STATE EDITOR. This will open the State Editor window.
2. Select "Use the HDL Design Wizard" and click OK.
3. In the Design Wizard Language window, select either ABEL or VHDL. We will be using the ABEL language. This implies that the State Editor will convert the graphical description into an ABEL code (or VHDL).
4. Specify the file name. Do not use names which are longer than 8 characters. Click NEXT.
5. In the Ports window, define the inputs: X, RST (for reset) and CLK (clock). Define also the output port Z. Click on the ADVANCED button and select the "Combinational" for the output direction. We will assume that the output of the sequence detector is coming from a combinational circuit. We could make the state machine synchronous by selecting "registered" for the output port Z (for ABEL). Notice that one needs to define a clock as one of the input ports. By naming one of the input ports CLK, the state machine determines that CLK is the clock input. We will also provide a reset signal, RST, that will allow us to reset the sequence detector to a known state. When all input and output ports have been defined click on the NEXT button.
6. In the "Machines" window, select "One" and click FINISH. The default name for the state register is Sreg0. This will open the State Editor window in which we can graphically describe our sequence detector, as shown in Figure 2. The top of the window shows the input and output terminals.

2. Defining the States

1. In the State Editor window, click on the State "S" icon on the left side vertical toolbar or select FSM-> STATE from the menu. This will place a state bubble in the window. You can reshape the bubble by selecting it and dragging the small squares. To rename the state click on the state name in the middle of the bubble and type the new name.  Add the three other states as shown in Figure 3.
    

   
    
   
   
   
   
   
   

   

   Figure 3: The four states of the sequence detector. (Screen clip from XilinxXACTstep(TM) Foundation software)

2. A state machine should have a reset so that it powers up in the correct state. This reset will not appear on the schematic but the presence of the reset in the state diagram will direct the HDL compiler to define the state encoding such that the machine starts in the correct state. To add the reset to the state diagram, click on the Reset icon (small triangle) on the left side toolbar or select FSM ->RESET. Place the reset symbol on the diagram. We want the machine to reset to the state S0. This is done by clicking inside the S0 state bubble. The reset can be synchronous or asynchronous. We will make the reset asynchronous. This can be done by right-clicking on the reset symbol and selecting "Asynchronous".

3. Defining the transitions
   A state diagram is defined by specifying under what conditions the input signal the machine goes from one state to another. These transitions are indicated by arrows between the state and by labeling the input conditions that causes the transition to occur as is shown in Figure 1 for our sequence detector. We will first define the transitions and then the conditions.
   1. Click on the Transition icon (icon with the arrow) on the left side toolbar (or select FSM -> Transition).
   2. Next, place the cursoor in the state S0 to start the transition. To create a bend in the arrow, place the cursor and click where you want the bend to occur. Then, click inside the state S1 to complete the transition. Do the same for all the transitions shown in Figure 1.
       
4. Defining the conditions

   
   The next step is to define the conditions associated with each transition (arrow).
    

   1. Click on the Condition icon (=?) or select FSM -> CONDITION.
   2. Click on the transition arrow, e.g. the transition between State S0 and S1. A small text box appears
   3. Enter the condition. If you use ABEL, you need to use the ABEL syntax to define the condition. For the transition from S0 to S1, type: X&!RST. Indeed the transition will occur when the input signal is "1" (i.e. X is true AND the Reset signal is negated). If you use VHDL type, X='0'.
   4. Do the same for all the other transitions. For instance, the transition between the Reset symbol and State S1 occurs under the condition: RST. Similarly, one stays in State S0 under the condition: !X#RST (i.e. when X=0 or the RST signal has been asserted). Notice that strictly speaking we don’t have to include the RST input in all the state transitions because we have included a Reset symbol. We have included it here to illustrate how to specify conditions with more than one input.

Figure 4 shows the state diagram with labeled transitions. You can select the conditions and move them around on the diagram.

5. Defining the Actions
    

   Actions (i.e. output signals) are either associated with transitions as is the case for a Mealy machine, or with a state as is the case for a Moore machine. In the example of our sequence detector (Mealy machine) we will associate actions with a transition.
    

   1. Click on the Transition Action icon on the vertical toolbar or select FSM -> ACTIONS -> TRANSITIONS.
   2. Click on the transition arrow. A text box will appear
   3. Type in the desired action. For the transition from S0 to S1, the output Z should go low. This is specified by typing: ^b0 in the text box, in case you use ABEL (for a VHDL based FSM, type Z<='0';). Do the same for all other transitions except for the transition from S3 to S1 which causes the output to go high: ^b1. In case multiple outputs are present you need to define each output. For intance: OUT1=0; SUM=0; or in case of a bus: OUTPUT_BUS=^b10.
   4. You can specify the clock signal (otherwise the State Editor will use the CLK signal you defined in the wizard. Select FSM -> MACHINE ->Sreg0. This will open the Machine Properties dialog box. Under General you can select the clock signal and specify to use the Rising or Falling edge of the clock. You can use this window to specify the reset signal, and the type of encoding  (Symbolic or Encoded such as binary, Gray of Johnson).

Figure 5a: Completed State Diagram of the sequence detector implemented as a Mealy machine using ABEL.
(Screen clip from XilinxXACTstep(TM) Foundation software)

In the previous example, it is not necessary to add the Reset signal at each transition. The same results would be obtained by only including the Reset signal at the transistion between the Reset icon and the S0 state, as shown in Figure 5b below.
 






Figure 5b: State Diagram of the (1011) sequence detector implemented as a Mealy machine using ABEL. The signal X is the input string.
(Screen clip from Xilinx (TM) Foundation software).

The same sequence detector can also be created using VHDL instead of ABEL. The state diagram of the (1011) sequence detector implemented as a Mealy machine with VHDL is shown in Figure 5c below.


Figure 5c: State Diagram of the (1011) sequence detector implemented as a Mealy machine with VHDL.
(Screen clip from XilinxXACTstep(TM) Foundation software)







An example of a  Moore machine that implements the same sequence detector is given further on.
 
 

6. Generating the HDL code and compiling the state diagram.

1. Save the state diagram
2. Specify the type of encoding to use for the states. Go to FSM -> MACHINE -> Sreg0. The Machine Properties window will open; select Binary encoding.
3. In case you would like to see the ABEL or VHDL code, go to SYNTHESIS -> HDL CODE GENERATION. A window will open showing the HDL Code. The ABEL code of the State Diagram of Figure 5b synthesized with  Binary Encoding or  Symbolic Encoding can be seen by clicking on the above links. The VHDL code for the state diagram with symbolic encoding can be seen by clicking  here.
4. At this point you can create a macro from the state diagram by going to the PROJECT -> CREATE MACRO menu. This will synthesize the state diagram and add it to the symbol libraries.
5. When you open the schematic editor you will be able to place the macro from the SC Symbol window. After placing the macro you can simulate it to verify the proper operation.
6. In case there are errors, you can view the report by going to SYNTHESIS -> VIEW REPORT. It can also be instructive to check the HDL Code (if you are familiar with specifying a state diagram in ABEL or VHDL).

7. Simulation and Implementation

   
   Once you have created a macro or synthesized the state diagram you can do a simulation. The functional simulation of the Mealy machine of the sequence detector is shown in  Figure 6. The output is valid at the end of the state-time which occurs just before the rising edge of the clock. The output is asserted after the sequence …1011. Notice that the output shows some glitches as is typical for an asynchronous Mealy machine. For a more detailed discussion of the output of the Mealy machine click  here. .
    
    
   
   

   

   Figure 6: Functional simulation of the Mealy sequence detector (sequence …1011).
   (Screen clip from XilinxXACTstep(TM) Foundation software)

   Graphical Simulation
   When you use for the encoding "Encoded (e.g. binary) " instead of Symbolic encoding you can follow the state transitions on the State Diagram during simulation. This is a good feature when debugging your state diagram. Start the simulator and define the signals. Next, open the state diagram; this can be done by using the Push Hierarchy button in the schematic editor. Once the State Editor window is open, go to TOOLS -> SIMULATION. This will activate the graphical simulation feature. The best is to have both the Waveform viewer and the State Editor window open so you can follow the state of simulation. The graphical simulation feature does not work for Mealy machines. An  example is given below for a Moore Machine sequence detector.

   When the circuit works properly you can implement it. Go to the Project Manager and click on the Implementation Icon. For more information about implementation consult the tutorial section in  implementation.
    

If one wants to eliminate the glitches in the output in the Mealy machine, one can implement the sequence detector as a Moore machine. The state diagram is given in Figure 7 below. One has to add one state, S4, as compared to the Mealy machine.

The corresponding state diagram description using the State Editor is given in Figure 8. The difference with the one of the Mealy machine, is that Actions are now associated with a State. These can be defined by clicking on Action State icon on the left vertical toolbar in the State Editor window (or by selecting FSM -> ACTIONS ->STATE).

In order to do a graphical simulation we will use Binary state encoding instead of symbolic encoding. Select FSM -> MACHINE ->Sreg0. In the Machine Properties window select Encode: binary. Click OK. To see the ABEL code, select SYNTHESIS -> HDL CODE GENERATION. To see the ABEL code click here.

We will do a functional simulation together with the graphical simulation of the State Machine. Start the simulator from the Project Manager window and select the signals and define the stimulators. Next, open the State Diagram by using the Push Hierarchy (H) button in the Schematic Editor window. From the State Diagram window, select TOOLS -> SIMULATION. The functional simulation of the Moore machine together with the state diagram is shown in Figure 9. The output goes high after the sequence 1011. No glitches are present in the output as compared to the Mealy machine (see Figure 6). Notice that the graphical editor can only be used when the State Editor is opened from the Project Manager or by using the Push Hierarchy in the schematic.

In the above example we created a Finite State Machine macro as part of a top-level schematic. However, a schematic project can have a top-level ABEL design created with the FSM editor (top-level ABEL designs are not recommended for FPGA projects). To add a top-level ABEL design to the project, do the following: in the State Editor, select FILE - SAVE; then select PROJECT -> ADD to PROJECT. Next, select SYNTHESIS -> SYNTHESIZE.

For more information about the State Editor, go to HELP -> STATE EDITOR HELP CONTENT in the State Editor Window.

1. Foundation Series 2.1i User Guide
2. Online Foundation Help.
3. D. Van den Bout, "The Practical Xilinx Designers Lab Book", Prentice Hall, Upper Saddle, NJ, 1998.

Copyright 1998,  Jan Van der Spiegel <jan@ee.upenn.edu>; Created November 15, 1998; Updated May 17, 2000.